1. Field of the Invention
The present invention relates to semiconducting integrated circuits (ICs), and more particularly to a method of fabricating a precision passive element, such as a resistor, capacitor, diode or transistor, on a semiconductor substrate. The present invention is also directed to the semiconductor structure that is fabricated from the method of the present invention.
2. Background of the Invention
In the fabrication of electronic ICs, processing variations often prevent the manufacture of precision passive elements such as, for example, resistors and capacitors. Moreover, the manufacturing controls on processes for forming passive elements in complementary metal oxide semiconductor (CMOS) chips fall far short of circuit design requirements. Industry standard input and output (I/O) specifications are tighter than that which can be achieved in current manufacturing processing. Manufacturing excessive chips and then sorting them for required parameters is one possible solution; however, this is a costly solution and it is not consistent with current manufacturing techniques.
Another solution to the above mentioned problem is to use fuses for trimming passive elements. The prior art teaches the method of trimming devices based upon a circuit test. In this method, a circuit is tested and then an appropriate circuit element is selected. In this case, a measurement and feedback loop is required as well as a fuse scheme. Moreover, elements remaining in the circuit after fuse trimming can cause unwanted parasitic capacitance since they remain attached to the main circuit although not active.
A third known solution to the aforementioned problem is to design active controls into the semiconductor circuitry to compensate for manufacturing variability. This approach is problematic since the active controls formed into the semiconductor circuitry takes up space. Moreover, this third approach increases complexity of fabricating the semiconductor circuitry, and it can lead to trade-offs in device performance.
Co-assigned U.S. Application Publication No. 2002/0113297, which is based on U.S. Ser. No. 09/525,088, filed Mar. 14, 2000, represents one current advancement in the art of fabricating precision circuit elements. In particular, the circuit elements are fabricated as part of an integrated circuit assembly. The processing of the circuit elements is such to provide a nominal circuit element value close in value to the desired value. Additional trim circuit elements are joined to the nominal circuit element through links. The links are fusible links or antifuses. By selectively blowing the fusible links or fusing the antifuses, trim circuit elements are added or subtracted to personalize the value of the nominal circuit element.
In more general terms, U.S. Application Publication No. 2002/0113297 discloses the formation of multiple devices, including one primary device containing additional trim elements, in parallel that can be selectively added or removed to dial into a targeted performance characteristic. The foregoing published U.S. Application, however, does not describe how to determine which devices to select. Moreover, the parallel circuitry employed in the foregoing published U.S. Application can lead to excess capacitance.
In view of the above, it is an objective of the present invention to provide a structure and method for providing precision passive elements that overcome the shortcomings of the prior art mentioned above.